High-Speed and Energy-Efficient Carry Look-Ahead Adder

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA not faster than other adders such as conditional sum (CSA), carry-select (CSLA), and Kogge–Stone (KSA), which fastest parallel-prefix adder. Further, in terms power-delay product (PDP) that characterizes energy digital circuits, efficient compared to CSLA KSA. In this context, paper presents energy-efficient architecture for CLA. Many ranging from ripple were implemented using 32-28 nm CMOS standard cell library by considering 32-bit addition. structurally described Verilog synthesized Synopsys Design Compiler. From results obtained, it observed proposed achieves reduction critical path delay 55.3% PDP 45% Compared CSA, 33.9%, power 26.1%, 51.1%. an optimized CSLA, 35.4%, area 37.3%, 37.1% without sacrificing speed. Although KSA faster, 39.6%, 6.5%, 55.6% comparison.